Nxfee Innovation

22/12/2023

Design of High Speed 8-bit Vedic Multiplier using Brent Kung Parallel Prefix Adder

20/12/2023

Design and Implementation of an 8-bit Approximate Wallace Tree Multiplier for Energy Efficient Deep Neural Network

Design and Implementation of an 8-bit Approximate Wallace Tree Multiplier for Energy Efficient Deep Neural Networks

19/12/2023

An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA

15/12/2023

FPGA Implementation of TFT 1.8 inch SPI 128×160 Display ROM Interface

FPGA Implementation of TFT 1.8 inch SPI 128x160 Display ROM Interface

08/12/2023

FPGA Implementation of Spread Spectrum Clock Generator with Onion Modulation

06/12/2023

An Efficient Image Encryption Algorithm Based on Innovative DES Structure and Hyperchaotic Keys

27/11/2023

An Innovative Area Efficient Pixel Shuffling Method for Image Encryption Algorithm

23/11/2023

A Lightweight True Random Number Generator for Root of Trust Applications

23/11/2023

Hybrid Protection of Digital FIR Filters

23/11/2023

Toward the Multiple Constant Multiplication at Minimal Hardware Cost

23/11/2023

Efficient Design of Behavioral Clock Divider for Multiple Frequency

23/11/2023

Design and Implementation of Arithmetic Logic Unit in HDL

23/11/2023

Smart Intelligent and Adaptive Traffic Controller using FPGA

23/11/2023

FPGA Implementation of Image Line Buffer to Split and reconstruct a 3×3 size of image pixel with using FIFO Design

FPGA Implementation of Image Line Buffer to Split and reconstruct a 3x3 size of image pixel with using FIFO Design

23/11/2023

FPGA Implementation of 64 Block Data Encryption Standard Algorithm

28/09/2023

Design of Approximate Restoring Divider

28/09/2023

Hamming based Single Fault Error Correction Code

28/09/2023

FPGA Implementation of High Performance Reversible logic based 16×16 Array Multiplier

FPGA Implementation of High Performance Reversible logic based 16x16 Array Multiplier

28/09/2023

FPGA Implementation of 8×8 Truncated Multiplier

FPGA Implementation of 8x8 Truncated Multiplier

25/08/2023

Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process

19/08/2023

Hardware Architecture for Adaptive Edge Directed Interpolation Algorithm

Hardware Architecture for Adaptive Edge Directed Interpolation Algorithm, Demosaicking, Carry Skip Adder, 256x256 image resolutions

01/08/2023

ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters

08/06/2023

Optimizing Ternary Multiplier Design with Fast Ternary Adder

Optimizing Ternary Multiplier Design with Fast Ternary Adder | Ternary Adder | Ternary Multiplier | Decimal to Ternary | Ternary to Decimal

08/06/2023

An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications

An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications | Approximate Multiplier | ECM | Image Multiplications

08/06/2023

Optimizing Ternary Multiplier Design with Fast Ternary Adder

Optimizing Ternary Multiplier Design with Fast Ternary Adder | Existing ternary multiplier designs are difficult to use in ternary systems. Thus, ternary Wa...

08/06/2023

An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications

An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications | Approximate computing is a promising paradigm for tradin...

17/05/2023

A VLSI-Based Hybrid ECG Compression Scheme for Wearable Sensor Node

A VLSI-Based Hybrid ECG Compression Scheme for Wearable Sensor Node | ECG | ECG Compression | Rice Coding | Golomb Rice Coding | Run Length Coding